An analog-to-digital converter (ADC) is a device that converts an analog input signal into a corresponding digital output signal. Typically, this conversion is performed by comparing the analog input signal to one or more reference voltages using one or more comparators. The results of these comparisons are then stored in memory units, such as latches or flip-flops. In most applications, the sampling of the input signal is performed at regular time intervals to generate a sequence of digital values representing the analog input signal.
FIG. 1 is a block diagram illustrating a simplified example of a one-bit ADC 100. In this example, the analog input signal is converted into one-bit digital samples at regular intervals defined by a clock signal.
Referring to FIG. 1, ADC 100 comprises a comparator 105 and a latch 110. Comparator 105 receives analog input signal Vin and compares it to a reference voltages Vref. In some implementations, where analog input signal Vin is greater than or equal to reference voltage Vref, comparator 105 outputs a “1”, and where analog input signal Vin is less than reference voltage Vref, comparator 105 outputs a “0”. Latch 110 stores the output of comparator 105 and outputs the stored value as a digital sample d0. The output of comparator 105 is updated according to a clock signal clk.
In general, the bit resolution of ADC 100 can be increased by performing additional comparisons between analog input signal Vin and other reference voltages and storing the results of the comparisons in additional latches. The additional comparisons can be performed in parallel using additional comparators, or they can be performed sequentially using the same or additional comparators. A simplified example of a multi-bit ADC that performs comparisons in sequence is described below with reference to FIG. 2.
FIG. 2 is a block diagram illustrating a simplified example of a successive approximation register (SAR) ADC 200. In this example, analog input signal Vin is converted into (n+1)-bit digital samples by performing “n+1” voltage comparisons at regular intervals defined by a clock signal clk.
Referring to FIG. 2, ADC 200 comprises a comparator 205, a SAR 210, and a digital to analog converter (DAC) 215. Comparator 205 receives analog input signal Vin and compares it to a reference signal Vref output by DAC 215. Where analog input signal Vin is greater than or equal to reference voltage Vref comparator 205 outputs a “1”, and where analog input signal Vin is less than reference voltage Vref, comparator 205 outputs a “0”. SAR 210 stores and outputs data d0, d1, . . . , dn using a corresponding plurality of latches, and it updates this data based on the output of comparator 205. For explanation purposes, it will be assumed that data d0 represents a most significant bit of a digital sample, data dn represents a least significant bit, and so on. DAC 215 converts the data d0, d1, . . . , dn into reference voltage Vref, so reference voltage Vref is updated with data d0, d1, . . . , dn. The updating of data d0, d1, . . . , dn and reference voltage Vref are performed according to clock signal elk, which controls the updating of the output of comparator 205.
During conventional switching operation of ADC 200, which is merely one of several potential implementations of an SAR ADC, data d0, d1, . . . , dn is updated by an iterative procedure in which comparator 205 performs successive comparisons between analog input signal Vin and reference voltage Vref according to clock signal elk. In the iterative procedure, data d0, d1, . . . , dn is initialized so that all bits are “0”. At the beginning of each iteration, data di is selected for updating, with “i” set to zero in the first iteration. Data di is changed to “1” and DAC 215 generates reference voltage Vref with a magnitude corresponding to data d0, d1, . . . , dn. For instance, where n=3, a first iteration changes data d0, d1, . . . , dn to “1000” and DAC 215 generates reference voltage Vref with a magnitude corresponding to “1000”. If analog input signal Vin is greater than or equal to reference voltage Vref, the value of data di remains at “1”. Otherwise, it is changed to “0”. Next, the procedure determines whether all bits of data d0, d1, . . . , dn have been updated. If so, data d0, d1, . . . , dn is fetched from the latches of SAR 210. Otherwise, “i” is incremented and a next iteration is performed.
In the above and other ADCs, the time needed to compare two analog voltages and store a resulting binary output value in a latch may depend on a difference between the two input voltages. The smaller the difference, the longer it takes for the output value to be generated and stored. A longer delay can potentially lead to metastability errors, causing the ADC to output erroneous results. For instance, in ADC 200 of FIG. 2, if the analog input signal Vin is relatively close to the initial value of reference voltage Vref a relatively long time may be required to update data d0. If this time is longer than the period of clock signal clk, data d0 will not be properly updated until a next comparison is performed, which can lead to a metastability error. An example of such a metastability error is described below with reference to FIGS. 3A and 3B.
FIG. 3A is a circuit diagram illustrating an example of a 4-bit SAR ADC 300. ADC 300 represents one possible implementation of ADC 200 of FIG. 2. FIG. 3B is a timing diagram illustrating the operation of ADC 300 and the generation of a metastability error during the operation.
Referring to FIGS. 3A and 3B, ADC 300 comprises substantially the same features as ADC 200, except that SAR 210 is implemented by a combination of a demultiplexer (DMUX) and a plurality of latches corresponding to data d0, d1, d2, d3, respectively. The DMUX operates responsive to a two bit control signal CTRL[0:1] to transfer the output of comparator 205 to one of four latches in the form of one of DMUX output signals D0, D1, D2, D3. For explanation purposes, it is assumed that analog input signal Vin has a magnitude corresponding to a digital value “0111”, as illustrated by a dotted horizontal line in FIG. 3B.
ADC 300 converts the analog input signal Vin into 4-bit data d0, d1, d2, d3 by performing four sequential comparisons every 1 ns at times t=0 ns, 1 ns, 2 ns, 3 ns, and the result is fetched at t=4 ns. Because analog input signal Vin has a value that is relatively close to the initial value of reference voltage Vref, a first comparison and storing can take more than 1 ns. In the example of FIG. 3B, it takes 2.5 ns. After 1 ns, ADC 300 stores data d0 as “1”, so a second comparison produces a “0”. After 2 ns, ADC 300 stores data [d0, d1] as “10”, so a third comparison produces a “0”. After 2.5 ns, the result of the first comparison is finally written to the corresponding latch, so ADC 300 stores data d0 as “0” at that time, as indicated by a dotted circle. After 3 ns, ADC 300 performs a fourth comparison, producing a “1”. A final result is “0001” instead of “0111”, which means the error magnitude is “0110”, which is almost a half-scale error for a 4-bit ADC. In other words, as illustrated by this example, metastability errors can produce relatively large conversion errors in an ADC.
In general, an ADC can be designed with reduced probability of metastability errors if the required conversion speed is relatively low. For instance, an ADC can be designed so that metastability errors occur with probability of 10−8. In measurement instrumentation applications, such as real-time oscilloscopes, however, the required metastability error rate may be extremely low (e.g., 10−20), and the required sampling speed may be extremely high (e.g., 10's or 100's GS/s). In these circumstances, the metastability error rate can be reduced by interleaving “M” ADCs, each operating at lower sampling speed (fs/M), but this can lead to an unacceptably large interleaving factor M. Moreover, some ADC architectures are more prone to metastability errors than others, i.e., errors occur more frequently for a given sampling speed. This is one reason why, for example, pipeline ADCs have been a preferred choice over an SAR ADCs, despite a generally superior power efficiency of SAR ADCs. This is also a reason why, for instance, asynchronous SAR ADCs have been faster than synchronous SAR ADCs, as there is no need to allot a large number of time constants to a comparator in an asynchronous SAR.
In view of the above and other shortcomings of conventional ADCs, there is a general need for ADCs having improved metastability detection and correction mechanisms.